Search results for "Power–delay product"

showing 3 items of 3 documents

A Methodology for the Design of MOS Current-Mode Logic Circuits

2010

In this paper, a design methodology for the minimization of various performance metrics of MOS Current-Mode Logic (MCML) circuits is described. In particular, it allows to minimize the delay under a given power consumption, the power consumption under a given delay and the power-delay product. Design solutions can be evaluated graphically or by simple and effective automatic procedures implemented within the MATLAB environment. The methodology exploits the novel concepts of crossing-point current and crossing-point capacitance. A useful feature of it is that it provides the designer with useful insights into the dependence of the performance metrics on design variables and fan-out capacitan…

EngineeringPower–delay productbusiness.industryCircuit designFan-outMOS current-mode logic MCML low-power design power-delay productSettore ING-INF/01 - ElettronicaCapacitanceElectronic Optical and Magnetic MaterialsLow-power electronicsElectronic engineeringCurrent-mode logicElectrical and Electronic EngineeringMATLABbusinesscomputerHardware_LOGICDESIGNcomputer.programming_languageElectronic circuitIEICE Transactions on Electronics
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Design of MOS Current Mode Logic Gates – Computing the Limits of Voltage Swing and Bias Current

2005

Minimizing a quality metric for an MCML gate, such as power-delay product or energy-delay product, requires solving a system of nonlinear equations subject to constraints on both bias current and voltage swing. In this paper, we will show that the limits of the swing and the bias current are affected by the constraints on maximum area and maximum delay. Moreover, methods for computing such limits are presented.

Power–delay productEmitter coupled logic circuitsBiasingSwingCMOS integrated circuitsComputer Science::Hardware Architecturemode logicComputer Science::Emerging TechnologiesLogic synthesisParasitic capacitanceControl theoryLogic gateHardware_INTEGRATEDCIRCUITSCurrent-mode logicHardware_LOGICDESIGNVoltageMathematics2005 IEEE International Symposium on Circuits and Systems
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Minimum power-delay product design of MCML gates

2008

This paper describes a methodology for the minimization of the power-delay product of MCML gates. The method is based on the novel concept of crossing point capacitance. The methodology was been validated by designing several gates using in an IBM 130 nm CMOS process.

Power–delay productbusiness.industryComputer scienceTransistorElectrical engineeringHardware_PERFORMANCEANDRELIABILITYCapacitancelaw.inventionLogic synthesislawLogic gateHardware_INTEGRATEDCIRCUITSElectronic engineeringCurrent-mode logicMinificationIBMbusinessHardware_LOGICDESIGN2008 International Conference on Signals and Electronic Systems
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